In semiconductor device manufacturing processes, a dual damascene method is frequently used for forming a multi-layer interconnection structure (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2002-83869). FIG. 20 comprises sectional views schematically showing sequentially ordered steps of a conventional process for forming an interconnection structure by use of a dual damascene method.
At first, for example, an interconnection layer 500, an inter-level insulating film 501, and an anti-reflective coating 502 are formed in this order on a substrate. Further, a first resist film 503 is formed on the surface of the multi-layer structure thus formed (FIG. 20, (a)). Then, patterning of the first resist film 503 is performed by a photolithography technique to form a predetermined pattern (FIG. 20, (b)). In this patterning step, the first resist film 503 is subjected to light exposure with a predetermined pattern, and the light-exposed portion is selectively removed by development. Subsequently, the anti-reflective coating 502 and inter-level insulating film 501 are etched by an etching process using the first resist film 503 as a mask. Consequently, a connection hole 504 is formed to extend from the surface of the multi-layer structure to the interconnection layer 500 (FIG. 20, (c)).
Thereafter, for example, the first resist film 503, which is not necessary any more, is peeled off and removed by an ashing process (FIG. 20, (d)). Then, a new second resist film 505 for forming an interconnection groove is formed (FIG. 20, (e)). Then, patterning of the second resist film 505 is performed by a photolithography technique (FIG. 20, (f)). Then, parts of the anti-reflective coating 502 and the inter-level insulating film 501 are etched by an etching process using the second resist film 505 as a mask. Consequently, an interconnection groove 506 is formed to be connected to the connection hole 504 and wider than the connection hole 504 (FIG. 20, (g)). Then, the second resist film 505, which is not necessary any more, is peeled off and removed (FIG. 20, (h)). Then, the connection hole 504 and interconnection groove 506 are filled with Cu material, so that a Cu interconnection line (including an interconnection layer and a via-plug) 507 is formed (FIG. 20, (i)).
In recent years, for interconnection structures of this kind, low dielectric constant materials (Low-k materials) including alkyl groups, such as methyl groups, as end groups are used as the material of the inter-level insulating film 501. In this case, etching damage tends to be caused to the inner surface portion of the connection hole 504 or interconnection groove 506, which has been formed by etching the inter-level insulating film 501. Further, when the first resist film 503 and second resist film 505 are removed after the etching process, the inner surface portion of the connection hole 504 or interconnection groove 506 is damaged. Due to this damage, the parasitic capacitance between interconnection lines is increased (due to an increase in dielectric constant), so a signal delay occurs and electrical characteristics, such as insulation resistance, are deteriorated. These problems bring about deterioration in the reliability of semiconductor devices, as circuit patterns used in semiconductor devices are increasingly miniaturized and highly integrated.